Senior Design Verification Engineer

Experience : 6 – 15+ Years

Location : (Bangalore / Hyderabad / Chennai / Pune / Noida / Kochi)

Band Level : B2 / B3 / C1

Job Type : Full-Time

Job Description :

We are looking for a highly skilled Senior Design Verification Engineer with a strong background in functional verification of complex ASIC / SoC designs. The ideal candidate should be experienced in building verification environments from scratch and be hands-on with industry-standard methodologies like UVM.

Key Responsibilities :

Develop and implement testbenches and verification environments using SystemVerilog / UVM .

Write test plans, test cases , and maintain functional coverage metrics.

Perform block-level and / or chip-level verification for IPs and SoCs.

Debug simulation failures and work closely with RTL designers to resolve issues.

Contribute to architecture discussions , bringing verification perspective.

Conduct regression tests, code reviews , and maintain high quality standards.

Required Skills :

Strong experience with SystemVerilog , UVM , and Verilog .

Hands-on experience in functional coverage , assertion-based verification , and constrained random testing .

Exposure to simulation tools like VCS , Questa , Incisive , etc.

Familiar with scripting (Perl, Python, Shell) for automation.

Knowledge of bus protocols like AXI, AHB, SPI, I2C , etc.

Experience working on complex SoCs, IP / Subsystem level verification .

Good debugging and analytical skills.

Preferred (Good to Have) :

Experience with formal verification tools (JasperGold, etc.).

Exposure to Emulation / FPGA prototyping .

Experience in low power verification and DFT-aware verification .

Familiarity with version control tools like Git / Perforce .

Education :

B.E / B.Tech or M.E / M.Tech in Electronics, Electrical, or VLSI Engineering .