Applications Engineering, Architect- STA

What You ll Need :

• BSEE / MS with minimum 15 years+ of relevant experience
• Proficiency in static timing analysis (STA) and advanced STA methodologies.
• Strong understanding of the full flow for chip design and EDA tools / flows.
• In-depth knowledge of 3DIC stacking, packaging, and their impact on timing analysis and closure.
• Experience with standard cells, MEM, IO IPs, and their library modeling and usage in flow.
• Proficiency in STA constraints, ECO, and power optimization flow.
• Hands-on experience with SPICE simulation and STA vs SPICE correlation.
• Knowledge of advanced CMOS technologies and FinFET technology at 5nm / 3nm / 2nm and beyond.
• Coding skills in TCL and Python; familiarity with C++ is a plus.
• Familiarity with industry-stand ard ASIC tools such as PT, ICC, Redhawk, and Tempus.

Who You Are :

Skills Required

Static Timing Analysis, Tcl Scripting, Python Programming, Application Engineering