Hi All,
Eximietas Hiring Senior Synthesis / Constraints.
Experience : 8+ Years.
Location : Bengaluru.
Block / Subsystem / Partition / Full chip.
- Role : Synthesis and Timing Constraint Engineer.
- EDA Tool : Cadence Genus & Fishtail.
- Node : TSMC 3nm / 5nm.
- UPF Implementation hands-on is must.
- Synthesis PPA optmimization, Hierarchical partition synthesis, Lint, Sanity Checks.
- Timing constraints generation and validation.
- Tcl, Perl, Python Scripting mandatory.
Interested Candidates please start sharing your resumes :