GLS Verification Engineer

Bachelor's or Master's degree in Electrical / Electronics / Computer Engineering or equivalent.

4+ years of experience in digital verification , with a focus on GLS .

Strong knowledge of Verilog / SystemVerilog , and SDF concepts.

Familiarity with EDA tools such as Synopsys VCS , Cadence Xcelium , Mentor Questa , etc.

Understanding of timing analysis , synthesis , and place & route (PnR) flow.

Experience handling X-checking , reset verification , and glitches in gate-level simulation.

Good debugging and problem-solving skills.

Strong scripting skills (Perl / Python / TCL / Shell).

Good communication and teamwork abilities.

Skills Required

Debugging, gls , systemverilog, Synthesis, Shell, Timing Analysis, Perl, Verilog, SDF, Problem-solving, Python, Tcl