Layout Design, Senior Engineer

Desired Skills :

• In depth familiarity with layout of analog and mixed signal CMOS circuits
• Exposure to Analog / Mixed Signal circuit layout (i.e RX, TX, PLL, etc..)
• Familiarity with Custom digital layout (i.e high speed logic paths)
• Aware of layout techniques to mitigate ESD, latchup
• Knowledge of layout effects (like matching, proximity effects etc)
• Knowledge of design for reliability (i.e EM, IR etc..)
• Knowledge of rules for advanced technology nodes across multiple foundries (SEC, TSMC, GF, Intel)
• Knowledge of DFM Rules for advanced technology nodes (16nm and below)
• Strong debugging, analytical and trouble shooting skills
• Excellent documentation and communication skills

Skills Required

Sec, Intel, DFM Analysis, Debugging, Analytical, Troubleshooting, CMOS