ASIC Design Engineer

LeadSoc Technologies is hiring!!

Senior RTL Engineers : 5-8 years

ASIC RTL Leads : 8 -12 years

Location : Bangalore

Exposure to subsystem or SOC level complexity involving connection and flows between components linked NOC, Peripherals, Microcontrollers.

Please share your profile to jhansi.bv@leadsoc.com for further discussion.