Immediate Start : Senior Design Verification Engineer

Job Title : Senior Design Verification Engineer

Location : Bengaluru, India

Experience : 5+ Years

Notice Period : Less than 30 Days

Job Description :

We are seeking a Senior Design Verification Engineer with 5+ years of experience in SoC / IP level verification. The candidate must have strong expertise in SystemVerilog, UVM methodology, testbench development, functional coverage, assertions, and debugging. Experience in verifying PCIe, Wireless protocols, or working with Formal Verification techniques is highly desirable. Strong knowledge of AXI / APB bus protocols and exposure to high-speed interfaces (USB, Ethernet, DDR, etc.) will be a plus. The role requires independent ownership, collaboration with cross-functional teams, and driving verification closure.

Requirements :

• 5+ years of Design Verification experience
• Hands-on expertise with SystemVerilog / UVM
• Experience in PCIe / Formal Verification / Wireless (any one is a strong advantage)
• Strong understanding of SoC / IP level verification
• Knowledge of AXI / APB protocols and high-speed interfaces
• Proficiency in simulation, regression, and coverage closure
• Available to join within 30 days