Physical Design (3-5)

Job Description : - Responsibilities Work with multiple SOC Design teams to rollout robust Logic Synthesis, UPF synthesis, QoR optimization and netlist Signoff flows

• Provide implementation flows support and issue debugging services to SOC design teams across various site
• Develop and maintain 3rd party tool integration and product enhancement routines
• Should lead implementation flow development effort independently by working closely with design team and EDA vendors
• Should drive new tool evaluation, methodology refinement for PPA optimization Skill Set
• Proficiency in Python / Tcl
• Familiar with Synthesis tools (DC / Genus), LEC, LP signoff tools
• Proficient in VLSI front end design steps- Verilog / VHDL, Synthesis, QoR optimization & Equivalence Checking
• Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus
• Should be sincere, dedicated and willing to take up new challenges Experience 3 to 5 years of experience in RTL,UPF & Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Timing Signoff Boolean Search Examples : ("RTL Design" OR "ASIC Design" AND (Synthesis OR HLS) AND (SDC OR FC))