Senior Emulation / Prototyping Engineer

Senior Emulation / Prototyping Engineers

Experience : 4-5 years

Location : Bangalore

experience in emulation / prototyping using Cadence / Synopsys tool flows (Palladium / Protium / HAPS / Zebu)

2. Working knowledge of System Verilog & Verilog language semantics and compilation flows

3. Solid understanding on SOC architecture and AXI protocol

4. Good communication skills and team collaboration

Interested,please drop your updated resume to janagaradha.n@acldigital.com