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Design Verification Engineer
7hillsTSbangalore, karnataka, in17 days ago
Job descriptionExperience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper. Experience in using one or more of revision control systems such as : Git, Perforce, Clearcase. Experience in SVA and formal verification is desirable (not a must) Script development using Python, Perl or TCL is desirable (not a must)
Exp : 8 to 15 Years
Location : Bangalore
Job Description :
- 8+ years of hands-on DV experience in SystemVerilog / UVM.
- Must be able to own and drive the verification of a block / subsystem or a SOC.
- Should have a track record of leading a team of engineers.
- Extensive experience in IP / sub-system and / or SoC level verification based on SV / UVM.
- Experience in Tesplan and Testbench development,
- Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time.
- Should be good with debugging and exposed to all aspects of verification flow including Gatesims
- Must have extensive experience in verification of one or more of the following :
o PCI Express or UCIe, CXL or NVMe
o AXI, ACE or CHI
o Ethernet, RoCE or RDMA
o DDR or LPDDR or HBM
o ARM or RISC-V CPU based subsystem or SOC level verification using C / Assembly languages
o Power Aware Simulations using UPF
Bangalore / Hyderabad / Kochi / Pune / Ahmedabad
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Design Verification Engineer • bangalore, karnataka, in