Software Test Automation Engineer

Role Overview

We are seeking an experienced STA + Synthesis Engineer with strong hands-on skills in Cadence Tempus for timing analysis and closure on complex SoC / ASIC designs. The candidate should have strong knowledge of constraints, synthesis flows, and timing debug.

Key Responsibilities

Perform RTL-to-Gate Synthesis using Genus / DC with high QoR.

Develop and optimize SDC constraints , clock definitions, and timing exceptions.

Execute Static Timing Analysis (STA) using Cadence Tempus and PrimeTime.

Drive timing closure across corners, modes, and hierarchical blocks.

Perform timing debug , ECO generation, and collaborate with PD teams for fixes.

Work with RTL designers to improve logic structure, timing robustness, and synthesis optimizations.

Develop scripts for better flow automation.

Required Skills

6+ years experience in STA and Synthesis for SoC / ASIC.

Expert in Cadence Tempus (mandatory).

Strong hands-on experience with :

Genus / Design Compiler

PrimeTime (PT)

STA signoff flows

Solid understanding of :

Timing concepts (setup, hold, OCV, ECO, multi-mode, multi-corner)

Clock tree structure , IO timing, integrated constraints

UPF / low-power flows (nice to have)

Proficiency in scripting ( TCL, Perl, Python )