STA Engineer

Job Description :

STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.

Timing analysis, validation and debug across multiple PVT conditions using PT / Tempus.

Run Primetime and / or Tempus for STA flow optimization and Spice to STA correlation.

Evaluate multiple timing methodologies / tools on different designs and technology nodes.

Work on automation scripts within STA / PD tools for methodology development.

Preferred Qualification / Skills-

Experince-3 years+

Strong expertise in STA timing analysis basics, AOCV / POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling.

Hands-on experience with STA tools - Prime-time, Tempus

Have experience working on timing convergence at Chip-level and Hard-Macro level.

In-depth knowledge crosstalk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,

Knowledge of ASIC back-end design flows, methods, and tools (ICC2, Innovus)

Knowledge of Spice simulation Hspice / FineSim, Monte Carlo. Silicon to spice model correlation.

Proficient is scripting languages – TCL, Perl, Python