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Design Engineer II
ConfidentialHyderabad / Secunderabad, Telangana9 days ago
Job descriptionBTech / MTech in Engineering with 2-5 years of practical experience in RTL Design. OR Equivalent Profound understanding of the end-to-end Digital design flow. Proficiency in Verilog / System-Verilog RTL logic design, debugging, and providing functional verification support. Knowledge of managing multiple asynchronous clock domains and their crossings. Familiarity with Lint checks and error resolution. Hands-on experience with APB and AXI protocols. Experience in micro-controller based designs and associated logic is advantageous. Additional experience in Digital microarchitecture definition and documentation is a plus. Exposure to synthesis timing constraints, static timing analysis, and constraint development is beneficial. Familiarity with FPGA and / or emulation platforms is advantageous. Strong communication skills, self-motivation, and organizational abilities are essential.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description :
- The selected candidate will be responsible for RTL Design and Verification & Integration, collaborating closely with Architects and the Verification team.
- Ensuring the required design quality through Lint and CDC checks and following release checklists.
Skillset / Requirements :
We're doing work that matters. Help us solve what others can't.
Skills Required
Static Timing Analysis, Fpga, Verilog, Rtl Design
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Design Engineer • Hyderabad / Secunderabad, Telangana