Description
We are seeking an experienced RTL Design Engineer to join our team in India. The ideal candidate will have 6-15 years of experience in designing and verifying RTL for complex digital systems. You will be responsible for creating high-quality RTL designs that meet performance and power specifications.
Responsibilities
- Design and implement RTL code for digital circuits using VHDL or Verilog.
- Perform functional verification of RTL designs using simulation tools.
- Collaborate with cross-functional teams to define design specifications and requirements.
- Optimize designs for performance, area, and power consumption.
- Debug and troubleshoot RTL designs and resolve any issues during the development process.
- Participate in design reviews and provide constructive feedback to peers.
Skills and Qualifications
Proficient in RTL design using VHDL or Verilog.Experience with synthesis tools such as Synopsys Design Compiler or Cadence Genus.Familiarity with digital design principles and methodologies.Knowledge of FPGA and ASIC design flows.Strong understanding of timing analysis and optimization techniques.Experience with simulation tools like ModelSim or QuestaSim.Ability to work collaboratively in a team environment and communicate effectively.Skills Required
Verilog, systemverilog, FPGA Design, Timing Analysis, Design Verification, low power design, digital logic