Design Verification Engineer

5+Yrs of Experience in Verification

Own UVM-based constrained-random verification for complex SoC / IP subsystems.

Develop testbenches, sequences, scoreboards, and checkers; close coverage (FC / CC / SC).

Must have SystemVerilog / UVM, assertions (SVA), functional coverage, and regressions.

Experience with bus protocols (AXI / AHB / APB / PCIe), cache / Coherency, and interrupts.

Debug with waveforms, CDC / RDC awareness, lint, and formal / property checks.

Tools : VCS / Questa / Xcelium, Verdi / DVE, Jenkins / CI, code reviews.

Strong scripting (Python / Perl / TCL), Make / CMake, version control (Git).

Work with architects / design / DFT / PD for spec clarification and sign-off