Digital Transformation Lead

Senior Digital Fault Tolerant Engineer

We are seeking an experienced Senior Digital Fault Tolerant (DFT) Engineer to lead the development of high-performance, next-generation System-on-Chip (SoC) and Application-Specific Integrated Circuit (ASIC) designs.

The successful candidate will have a strong background in DFT strategy and architecture, with expertise in scan insertion, compression, ATPG, MBIST, and boundary scan. They will be responsible for defining and driving DFT strategies and architectures for multiple projects, leading implementation and verification of DFT features, and collaborating with cross-functional teams to ensure seamless integration.

Requirements

• Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design
• At least 7 years of experience in DFT for complex ASIC or SOC designs
• Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan
• Familiarity with DFT tools such as Synopsys DFT Compiler, TetraMAX, TestMAX, Siemens EDA Tessent ScanPro, MBIST, IJTAG, Cadence / others Modus, Encounter Test
• Strong knowledge of RTL design, STA, and synthesis flows
• Proficient in scripting languages for flow automation

What We Offer