Memory Layout Engineer

Exp : 3 to 8 Years

Location : Bangalore

Notice : Immediate - 15 days

✅ Memory Leafcell layout library design from scratch including top level integration.

✅ Good knowledge on different types of memory architectures.

✅ Good knowledge in optimized layout design for better performance.

✅ Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations.

✅ Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions.

✅ Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow