Power Management Subsystem Architect

We’re looking for a hands-on RTL Design Engineer to own the microarchitecture and RTL implementation of the Power Management Subsystem . You’ll collaborate with cross-functional teams—architecture, firmware, software, DV, and PD—to define, design, and optimize power management solutions for next-generation RISC-V / ARM-based SoCs.

This role is hybrid, based out of Bangalore, India. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• 10–12 years of experience in ASIC design, with expertise in microarchitecture and RTL for complex subsystems
• Skilled in Verilog / SystemVerilog and comfortable working across design, debug, and analysis
• Deep understanding of power management concepts—clocking, reset, DVFS, and low-power modes
• Familiar with RISC-V or ARM-based SoCs and standard bus protocols (AXI, AHB, APB, CHI)
• Awareness of functional safety (ISO 26262) practices in hardware design

What We Need

What You Will Learn