Design Verification

Key Responsibilities :

Develop and execute verification plans for SoC and NoC architectures.

Write and maintain test benches using SystemVerilog / UVM.

Perform functional, performance, and power verification.

Debug and resolve design and verification issues.

Work with high-speed interconnect protocols (AXI, CHI, PCIe, Ethernet, CXL, UCIe).

Work closely with design and architecture teams to ensure compliance with specifications.

Strong hands on verification experience in L2 / L3 / SLC / LLC

Strong understanding of coherence and related protocols

Collaborate with design, applications, product and test engineering teams to ensure the implementation meets both architectural and micro-architectural intent for complex IPs and feature areas of subsystem and SoC.

Experience in CPU(preferably ARM) based verification, C / C++ and / or hardware verification languages e.g. (SystemVerilog), shell programming / scripting (e.g. Tcl, Perl, Python etc.)

Exposure to all stages of verification requirements collection, creation of test plans, testbench implementation, test cases development, documentation and support.

Experience in verification of SoC Debug components - DAP, Trace, ELA etc

Experienced in one or many of these technologies / protocols – DDR, HBM, PCIe, CXL, Ethernet, Coherent Interconnects and RAS.

Skills Required

System Verilog, Uvm, AMBA, Soc, Pcie