Senior ASIC RTL Designer

Position : ASIC RTL Design Engineer

Location : Bangalore / Hyderabad

Experience : 6+ years

Design and develop synthesizable RTL using Verilog / SystemVerilog for complex ASIC / SoC blocks.

Create micro-architecture specs and ensure designs meet performance, power, and area targets.

Own RTL implementation, lint / CDC cleanup, and contribute to synthesis, STA, and DFT readiness.

Collaborate with verification teams for test planning, debugging, and coverage closure.

Integrate IPs into top-level SoC and resolve timing and functionality issues.

Support emulation, FPGA prototyping, and silicon bring-up activities with cross-functional teams.