Design for Testability Lead

DFT Lead - 7 to 15 Years

Job Location : Bangalore| Hyderabad | Noida | Ahmedabad | Chennai

(NO WORK FROM HOME OR REMOTE WORK)

Job Specs :

• In depth knowledge of DFT concepts
• In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis
• In depth knowledge and hands on experience in MBIST insertion and Memory test validation
• Expertise in test mode timing constraints definition, knowledge in providing timing fixes / corrective actions for timing violations
• Expertise in scripting languages such as perl, shell, etc.
• Experience in RTL and Gate level simulations of scan and MBIST test vectors
• Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TetraMax)
• Working experience in Synopsis TetraMax / DFTMax and Cadence Encounter Test is a plus
• Ability to work in an international team, dynamic environment
• Ability to learn and adapt to new tools and methodologies.
• Ability to do multi-tasking & work on several high priority designs in parallel.
• Excellent problem solving skills
• Excellent communication and team work skills and good English is required