Description:
Our client is looking for an RTL Design Engineer to join their team. This is a direct and permanent opportunity.
Job Description:
We are looking for an experienced RTL Design Engineer to develop high-quality RTL, drive IP/subsystem integration, and ensure design readiness through rigorous quality checks including Lint, CDC, RDC, synthesis, and handoff validation.
Skills Required:
- Strong experience developing synthesizable RTL using Verilog/SystemVerilog.
- Experience working on complex digital IPs and SoC subsystems.
- Ability to translate architecture specifications into scalable microarchitectures.
- Experience integrating IPs and AMBA interfaces, including:
1. AXI4, AXI4-Lite, AHB, APB
- Strong understanding of RTL coding standards and design methodologies.
- Experience with RTL reviews and design quality assessments.
- Hands-on experience with:
1. Lint, CDC, RDC
2. X-propagation
3. Synthesis
4. Structural checks
5. Design-rule checks
- Experience with clock/reset handling, address mapping, and configuration.
- Strong debugging and problem-solving skills.
- Experience developing automation, dashboards, and quality metrics is an Develop RTL from architecture interpretation through design handoff.
- Perform IP integration, clock/reset handling, address mapping, and configuration.
- Conduct detailed RTL reviews and quality assessments.
- Identify and drive closure of functional, structural, and methodology issues.
- Analyze and resolve Lint, CDC/RDC, X-propagation, synthesis, and structural violations.
- Collaborate with architecture, design, and verification teams.
- Ensure RTL handoff readiness through clean signoffs.
- Ensure protocol compliance and register-spec alignment.
- Validate clock/reset architecture.
- Develop and enhance design automation and quality methodologies.
- Build automated checks, regression analysis, dashboards, and team-level quality gates.
Key Technologies:
- HDL: Verilog, SystemVerilog
- Protocols: AXI4, AXI4-Lite, AHB, APB
- RTL Quality: Lint, CDC, RDC, X-Propagation, Synthesis
- Design: IP Integration, SoC, Digital Design, Clock/Reset, Address Mapping
- Automation: Regression, Dashboards, Quality Metrics
(ref:hirist.tech)
RTL Design Engineer • Hyderabad
Electronics and Electrical Engineering from an institute of repute.Analog and SERDES IP Circuit Design.The candidate should have relevant experience in following Analog IPs like GPIO, RCOMP, ADC, D... Show more
Job Title: RTL Design Engineers.You'll debug simulation failures, implement ECOs, and support gate-level simulations.Collaborate with cross-functional teams (SW, DV, Physical Design) to achieve tap... Show more
AMS Circuit Design Engineer Experience: 2 to 8 Years.Electronics and Electrical Engineering from an institute of repute.Analog and SERDES IP Circuit Design.The candidate should have relevant experi... Show more
Design Engineer - PPRTL / Prime Power.Experience in ASIC design flow and EDA tools experience such as PPRTL, PowerArtist and PrimePower or other power analysis/simulation tools.Analyze design metri... Show more
Job Title: RTL Design Engineers.Loctaion: Hyderabad /Bangalore.Top-level (SOC) level basic industry standard Arch knowledge.SoC & IP level Integration knowledge.IORING and Phys & GPIOs basic functi... Show more
SSOC Design Verification Engineer - Senior / Lead / Sr.Must have good knowledge on the verification flows.Excellent hands-on debug skills and problem solving attitude.Experience of working in compl... Show more
Design Engineer - PPRTL / Prime Power Job Description: Experience in ASIC design flow and EDA tools experience such as PPRTL, PowerArtist and PrimePower or other power analysis/simulation tools Ana... Show more
An emerging value provider across an array of digital transformation solutions to address on-demand security and governance needs.Founded in 2010, the footprints of ISSQUARED span across the pillar... Show more
