Gate Level Simulation Design Verification Engineer

Job Title : Gate Level Simulation (GLS) Design Verification Engineer

Experience : 7-10 Years (Minimum 5 years of hands-on Gate Level Simulation experience)

Job Location : Bengaluru | Visakhapatnam (Vizag) | Kochi | Ahmedabad

Employment Type : Full-Time

Job Summary :

We are looking for experienced Design Verification Engineers with strong expertise in Gate Level Simulation (GLS) SystemVerilog | UVM | PCIe to validate complex ASIC, SoC, and IP designs. The ideal candidate should have hands-on experience in RTL and GLS verification, UVM-based verification environments, debugging simulation failures, and regression automation.

You will collaborate closely with Design, Architecture, Physical Design, and Validation teams to ensure high-quality silicon and first-pass success.

Key Responsibilities :

- Perform RTL and Gate Level Simulation (GLS) for ASIC/SoC/IP verification.

- Develop directed and constrained-random test cases using System Verilog and UVM.

- Create and execute comprehensive verification plans.

- Debug simulation failures and identify root causes across RTL, testbench, and EDA tools (VCS, Verdi).

- Analyze and resolve Gate Level Simulation timing and functional issues.

- Automate regression flows and improve verification productivity using scripting.

- Work closely with Design and Physical Design teams to resolve verification issues.

- Ensure functional correctness and verification closure before tape-out.

Required Skills :

- Minimum 5+ years of hands-on experience in Gate Level Simulation (GLS).

- Strong expertise in System Verilog.

- Experience in ASIC/SoC/IP Verification.

- Hands-on experience with Universal Verification Methodology (UVM).

- Experience in RTL and Gate Level Simulation.

- Strong debugging skills for RTL and GLS issues.

- Experience with Synopsys VCS and Verdi.

- Good understanding of PCI Express (PCIe) protocol.

- Proficiency in Python, Perl, or Shell scripting for automation.

Preferred Skills :

- Knowledge of regression automation and verification methodologies.

- Strong analytical and debugging skills.

- Exposure to timing-aware simulations and GLS best practices.

- Good communication and collaboration skills.

Education :

B.E./B.Tech/M.E./M.Tech in Electrical Engineering, Electronics Engineering, Electronics & Communication, VLSI, or a related discipline.

(ref:hirist.tech)