Lead EMIR Synthesis Position at Bangalore

About the Company

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and healt

h.

The Cadence Advan

• tage
  
  The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an i
• mpact.Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the empl
• oyees.The unique 'One Cadence – One Team' culture promotes collaboration within and across teams to ensure customer su
• ccess.Multiple avenues of learning and development available for employees to explore as per their specific requirement and inte
• rests.You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—ever

y day.

About

the Role

Job location: Bangalore. Major responsibilitie

s include:

Resp

• onsibilities
  
  Benchmarking technology nodes, pdks, libraries through synthesis, place and route and EMIR analysis of va
• rious designs.Pull out various metrics from the runs and make a qualit
• ative summary:Explaining the PPA trends seen across various stage
• s of the runs.Correlate with device level and gate
• level trends.Identify performance bottlenecks for each library
• architecture.Qualitative feedback to library team on architecture and cell
• design/layout.Come up with proposal for new cells to im
• prove the PPA.Identify any EDA enhancements needed to get the best PPA out o
• f the library.Update the P&R validation (library validation) and benchmarking flows to meet e
• volving needs.It is highly expected that the role requires usage of AI tools/resources at disposal to execute these responsibilities for achieving highest efficienc
• y and quality.The role requires extensive interaction with library architect, design, modelling and routing tech files teams, EDA teams and other internal implementation a

nd flow teams.

• 
  
  Qualifications
  
  Bachelors/Maste
• rs in Electronics.5-8 years experienced in synthesis, P&R benchmarking, power i

ntegrity analys

• is.
  
  Required Skills
  
  Very good understanding of standard cell library design and library EDA views a
• nd routing tech files.Experience in advanced technology nodes
• (5nm, 3nm, 2nm, 14A).Proficiency in Cadence tools (Genus, Innovu
• s, Voltus) preferable.Pro-active approach to work and pr
• oblem-solving ability.Teamwork with engineers in other design centers sp

read across the

• globe.
  
  Preferr

ed Skills

None specified.
Skills Required
Synthesis, Cadence Tools