Senior Manager, Design Verification Engineering

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Senior Manager, Design Verification
The Engineering Enablement team provides industry-leading tools, methodologies, and support to accelerate product development across the company. This position is part of the Digital Systems IP team within the Engineering Enablement organization. The IP team builds, curates and guides the development of IP across ADI.

We’re seeking a highly experienced, seasoned DV expert with experience in leading DV efforts for verification of different IP components and subsystems from scratch.

About the role
In this position the successful candidate will lead and be exposed to the entire product lifecycle from concept phase, through design, verification, implementation, and release of IP to various product teams. They will collaborate with the wider ADI technical community, which affords an opportunity to work with many business units in ADI with exposure to many technologies and products. This is a senior role with the opportunity to create real impact within the organization and build a promising career.

Responsibilities

• Verification of complex Digital designs and sub-systems using leading edge verification methodologies.
• Manage and mentor a high performing team of DV engineers, plan the DV strategy, manage the execution
• Defining verification strategy, test plans, tests and verification methodology for chip-level verification.
• Interact with various BU teams that use or explore ADIP IP. Understand the SoC use cases and enhance DV to support them
• Working with the design team in generating test-plans and closure of code and functional coverage
• Continuous interaction with Design, Architecture and Firmware teams
• Tracking and management of design verification improvements
  

Required Qualifications

• Bachelor’s or Master’s degree in Electronic Engineering or a related field, with at least 15 years of ASIC design verification experience.
• Experience managing teams of 20 or more people.
• Strong leadership skills with the ability to define and execute verification strategies.
• Proven ability to communicate effectively with peers, managers, and project stakeholders in both written and verbal formats.
• Broad expertise in digital verification, including constrained-random verification, functional and code coverage, assertion-based methodology, formal verification, analog behavioral modeling, SystemVerilog real-number modeling, behavioral model validation, and mixed-signal simulators such as Cadence Xcelium.
• Experience applying AI tools to design verification workflows.
• Experience with processor-based verification and gate-level simulation flows for SoC verification.
• Proficiency in Verilog, C/C++, SystemC, Java, TCL, Perl, Python, and shell scripting.
• Experience with Property Specification Language (PSL), MATLAB, including co-simulation and HDL generation, and digital signal processing is a plus.
• Experience with low-power methodologies such as CPF and UPF is a plus.
• Excellent interpersonal and communication skills, with enthusiasm for taking on diverse challenges.
• Self-motivated and enthusiastic.