Physical Design Engineer – ASIC/SoC

HCLTech is a leading global technology company, recognized for delivering cutting-edge digital, engineering, and cloud solutions to enterprises worldwide. With a strong presence in over 50 countries and a workforce of more than 220,000 professionals, HCLTech has consistently been at the forefront of innovation, leveraging its deep domain expertise and robust R&D capabilities. The organization is committed to driving customer success through a culture of collaboration, integrity, and continuous learning, and has been repeatedly acknowledged among the top employers and most innovative technology providers globally.

Overview of the Role

As a Physical Design Engineer at HCLTech, you will play a pivotal role in the end-to-end implementation of advanced ASIC/SoC designs. You will be responsible for delivering high-quality, power-optimized, and timing-closed layouts for state-of-the-art semiconductor products, working closely with cross-functional teams to ensure first-time-right silicon. This role offers an opportunity to contribute to high-impact projects that drive the next generation of technological advancements in the semiconductor industry.

Detailed Responsibilities:

• Execute and optimize floorplanning, power planning, placement, clock tree synthesis (CTS), and routing for complex ASIC/SoC designs.
• Perform physical verification tasks including layout versus schematic (LVS), design rule check (DRC), and electrical rule check (ERC) using industry-standard tools such as Calibre.
• Implement and manage Engineering Change Orders (ECOs) and ensure efficient design modifications.
• Drive timing closure efforts, including multi-corner multi-mode (MCMM) analysis, using tools such as PrimeTime and Tempus.
• Conduct Static Timing Analysis (STA), setup/hold analysis, signal integrity (SI) analysis, crosstalk analysis, and manage on-chip variation (OCV, AOCV, POCV).
• Develop and validate Synopsys Design Constraints (SDC) and TCL scripts for automation and verification.
• Perform IR drop and Electromigration (EM) analysis to ensure design reliability and sign-off for advanced technology nodes.
• Collaborate with design, verification, and test teams to resolve complex design challenges and ensure project milestones are met.
• Prepare documentation, reports, and participate in design reviews to communicate and justify design decisions.

Skill Requirements:

• Bachelor’s or Master’s degree in Electronics Engineering, Electrical Engineering, VLSI Design, or a related field.
• 7 to 14 years of hands-on experience in physical design for ASIC/SoC projects, including experience with advanced process nodes.
• Proficiency with industry-standard EDA tools: Synopsys ICC2, Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, Tempus, Calibre, etc.
• Strong expertise in floorplanning, power planning, placement, CTS, routing, and physical verification.
• Solid understanding of STA, MCMM, setup/hold analysis, SI analysis, crosstalk, OCV, AOCV, POCV.
• Experience in scripting (TCL, SDC) for design automation.
• Proven track record of successful timing closure and physical sign-off.
• Excellent analytical, problem-solving, and communication skills.

Other Requirements (Optional):

• Experience with IR drop and EM analysis tools and methodologies.
• Familiarity with low-power design techniques and methodologies for advanced technology nodes (e.g., 7nm, 5nm, below).
• Knowledge of RTL-to-GDSII flow and cross-functional collaboration with logical design and verification teams.
• Relevant industry certifications in VLSI/Physical Design will be an advantage.

Career Development Opportunities:

• Access to world-class training programs, certification courses, and knowledge-sharing platforms to support continuous learning and professional growth.
• Opportunity to work on cutting-edge semiconductor projects for global clients, expanding technical expertise in advanced nodes and EDA tools.
• Clearly defined career pathways, with opportunities to advance into technical leadership, project management, or specialized expert roles within the organization.
• Exposure to international assignments, cross-functional teams, and a diverse, inclusive culture that fosters innovation and leadership development.
• Performance-driven rewards, recognition, and mentorship programs designed to nurture talent and support long-term career ambitions at HCLTech.