DFT Engineer

Job Description :

- Scan chain insertion and compression (Tessent) across multi-clock digital logic.

- ASA PHY DFT integration.

- ASA IP DFT ports.

- BIST PCS-PMA bus isolation.

- Memory BIST (MBIST) for internal SRAMs/FIFOs; ATPG pattern generation and fault simulation.

- IEEE 1149.1 JTAG controller integration; boundary scan for automotive test coverage.

- Siemens Tessent or Synopsys DFT Compiler; prior automotive-grade DFT (AEC-Q100) experience preferred.

- The coverage requirement for DFT modes will be specified by SiliconAuto.

About the Role :

The successful candidate will be responsible for integrating DFT solutions into digital logic designs, ensuring that all aspects of the design are properly tested and validated. This will include working with various IP blocks, such as ASA PHY and ASA IP, as well as integrating boundary scan and JTAG controllers for automotive test coverage.

Key Responsibilities :

- Scan chain insertion and compression across multi-clock digital logic using tools such as Siemens Tessent

- Integrate ASA PHY DFT and ASA IP DFT ports

- Implement BIST PCS-PMA bus isolation and memory BIST for internal SRAMs and FIFOs

- Generate ATPG patterns and perform fault simulation

- Integrate IEEE 1149.1 JTAG controllers and implement boundary scan for automotive test coverage

Required Skills :

- Experience with DFT tools such as Siemens Tessent or Synopsys DFT Compiler

- Knowledge of digital logic design and test principles

- Understanding of automotive-grade DFT requirements, including AEC-Q100

- Strong problem-solving and analytical skills

(ref:hirist.tech)