Manager, Design Verification

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Role Overview

The Lead Physical Design Engineer is role which combines deep hands-on implementation expertise with technical leadership. This role owns complex block- and/or top-level physical design for advanced-node SoCs and leads a small group of engineers to achieve high-quality, on-time delivery.

Key Responsibilities

Technical Ownership

Own end-to-end physical implementation (floorplanning, power planning, placement, CTS, routing, ECO) for complex blocks or subsystems across advanced technology nodes (e.g., 22nm, 16nm, 7nm, 5nm, 4nm).

Drive timing closure, congestion resolution, IR/EM, signal integrity, and physical verification (DRC/LVS/antenna) to meet PPA and quality targets.

Define and refine hierarchical PNR strategies, IO ring/PG structures, and integration guidelines for large SoCs.

Perform in-depth analysis and debug of tool issues, timing failures, and physical design anomalies; propose robust, scalable solutions.

Methodology and Automation

Develop, maintain, and enhance physical design methodologies, scripts, and flows (e.g., for PDN, PG, clock structure, exception handling, signoff automation).

Proactively identify opportunities for flow improvements and standardization to reduce turnaround time and error rates.

Evaluate EDA tool features and drive best practices in collaboration with CAD/enablement teams.

Technical Leadership & Team Enablement

Provide technical direction to a small group of physical design engineers, including task breakdown, priority setting, and quality expectations.

Mentor junior engineers and NCGs in PNR, STA and debug practices to build a strong second tier of technical capability.

Review floorplans, constraints, and implementation choices from team members, giving clear, actionable feedback.

Act as a go-to technical reference within the PD team.

Cross-Functional Collaboration

Work closely with RTL design, STA, DFT, CAD, and packaging teams to converge on implementation-friendly architectures and constraints.

Communicate risks, options, and trade-offs clearly to project leads and managers, and help shape mitigation plans.

Participate in design reviews and signoff reviews, representing physical design status, risks, and recommendations.

Required Qualifications

Strong experience in physical design implementation for complex digital SoCs, typically 8–12+ years in physical design or equivalent level of mastery.

Proven hands-on expertise with industry-standard PNR and signoff tools (e.g., Cadence Innovus, Synopsys ICC2, Tempus/PrimeTime, RedHawk, Voltus, etc.).

Demonstrated success in closing challenging blocks/subsystems on advanced nodes (timing-, IR-, and congestion-critical designs).

Solid understanding of:

Floorplanning and partitioning strategies

Power grid and PDN methodology (including IR/EM mitigation)

Advanced clock tree/clock mesh design and constraints

STA constraints (modes/corners, exceptions, derates)

Physical verification and reliability checks

Leadership Expectations

Strong problem-solving and debugging mindset, with a bias toward scalable, automated solutions.

Clear, concise communication skills—able to explain complex technical issues and options to different audiences.

Demonstrated commitment to mentoring, knowledge sharing, and raising the capability of the broader team.

Comfortable operating in a dynamic environment with shifting priorities while maintaining quality and accountability.