Senior SoC PD Lead

Senior SoC PD

FULL-TIME

15+ Years of exp

Location : Bangalore / Hyderabad

Job Description

We are seeking a highly accomplished Senior SoC PD Design to drive highly sophisticated SoC designs for our global semiconductor Custom Silicon group. Projects are getting executed in advanced semiconductor nodes e.g 8nm, 5nm, 3nm. This role centers on technical vision, engineering depth, and cross-regional collaboration, executed jointly by teams in India and Europe. The ideal candidate is a proven PD leader capable of guiding distributed engineering organizations toward innovation, best-in-class quality, and first-pass silicon success

You will play a key role in our projects and interact with the design, verification and physical design team as well as with international customers.

This position offers the opportunity to work on cutting-edge technologies for our highly complex SoC and image pipeline development projects.

Responsibilities

• Capturing of the Physical design requirements of complex SoCs working with SoC Architects. This includes the technical evaluation technology, Interaction with internal and external IP providers to align with the customer requirements of Floorplan, Area, Design closure and Signoff in a wide spectrum of applications in the automotive, industrial or commercial context
• Support the technical discussions with customers for the alignment of requirements, keeping track of implementation as well as power-performance-area restrictions. Support of our Arch, Design and PD teams in technical discussions already in the project acquisition and delivery phase
• Writing of Physical design requirements and design constraints towithther with our team of architects, design, packaging and DFT. Typically accompanying the complete Lifecyle with direct contact to our Design, Test and Packaging Teams as well as being close contact to the project management
• Perform detailed calculations to specify area, utilization, power budgets and support performance v/s area v/s power tradeoffs
• Collaborate with PDK, Foundry and design teams to ensure that the ASIC meets the required area and power goals
  
  

Our Company

Tessolve Semiconductors a venture of Hero Electronix, part of $5B Hero Group companies a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions. Currently we are 3800+ employees worldwide.

We are Global Multi- National Company having Engineering and Sales presences in India, Malaysia, Singapore, USA, UK, Europe, and China. Tessolve has strategic and sustainable growth plan to ensure the business stability to our valued customers and to protect the career of our employees even under disturbed Business situations.

About You

You are highly motivated, not afraid of taking responsibility, and you are a team player. Besides having excellent problem-solving and analytical skills, you are an efficient professional, and you like to help extending our organization for further growth.

Qualifications

• Master s or PhD degree in Electrical Engineering, Electronics Engineering or comparable
• Minimum 15 years of experience in Digital ASIC architecture and proficient in Floorplan, Clock Plan, P&R Flow, DRC, LVS and Tapeout Signoff.
• Used to work in a customer-oriented, self-reliant, extremely reliable and structured manner and able to collaborate with international development teams
• Strong interest in SoC PD Flows with embedded AI engines and desire to improve SoC PD flows till. Good understanding of advanced technology nodes like 8nm, 5nm, 3nm, design partitioning and decent timing and signoff closure challenges across different technologies
• In depth IP knowledge for Floorplan, Clocking, Design partitions and Timing closure
• Deep working experience with PDK and Foundry teams is an advantage
• Knowledge on the special aspect of functional safety (ISO 26262) is an advantage
• Fluent in English, both written and spoken.
• Excellent written and verbal communication skills

Skills Required
Floorplan, LVS, PDK