Description :
- Good knowledge of SystemVerilog
- Hands-on experience with UVM (Universal Verification Methodology)
- Experience with EDA tools (e.g., VCS, Verdi)
- Experience in debugging RTL and gate level simulation issues
- Experience in PCIe/Ucie/ethernet/DDR
- 7+ years of experience in Design Verification, with recent experience in a lead/ownership role
- Deep expertise in System Verilog, UVM, and functional verification methodologies
- Strong hands-on with testbench development, assertions, coverage-driven verification, and debug
- Exposure to IP/Sub-system/SoC-level verification
- Proficient in simulation tools (VCS/Questa/Xcelium), waveform viewers, coverage tools
- Experience in building and managing teams
- Good understanding of design concepts, synthesis, and verification flows
- Strong problem-solving, communication, and leadership skills
- Familiarity with protocols like AXI, AHB, PCIe/USB/Ethernet/LPDDR/CXL/PMC, etc.
- Knowledge of scripting (Python/Perl/TCL) for flow automation
- Good to have experience in formal verification or low power(UPF) flows
(ref:hirist.tech)