Layout Design Engineer

Job Role: Layout Design Engineer

Work Location : Hyderabad (WFO)

Experience: 5 to 8 Years

Budget: 20 LPA

Mode of Hire: Fulltime with OTSI

Notice Period: Immediate to 30 days (max)

Mandate Skills:

• Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support

• TSMC 3nm Exp – MANDATORY

• custom layout or analog layout with TSMC 3nm/5nm7nm/16nm Finfet & 5+ exp

Responsibilities:

• Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support.

• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.

• Perform layout verification like LVS/DRC/Antenna, quality check and support documentation.

• Responsible for on-time delivery of block-level layouts with acceptable quality.

• Excellent problem-solving skills in physical verification of custom layout.

• Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment.

• Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items.

• Contribute to effective project-management.

• Effectively communicating with Local engineering teams to assure the success of layout project.

Educational Background:

• BE or MTech in Electronic/VLSI Engineering

• 5 + year experience in analog/custom layout design in advanced CMOS process.

Pointers to be Considered:

1. Candidate needs to be very clear about basic concepts.

2. He/She is expected to be really good at problem solving.

3. The candidate has to be able to challenge traditional way of doing layouts ( Out of the box approach is needed ).

4. Candidate needs to be able to work independently with minimal inputs.

• 5. Dedication, commitment and flexibility are very critical to achieve tight timelines without compromising on quality of delivery.

Skills Required
LVS