Dft Engineer

🔍 Role : DFT Engineer (Design for Testability)

📍 Location : Noida

💼 Experience : 7–10 years

💰 Budget : Open / As per company standards

🎓 Qualification : BE / ME / B.Tech / M.Tech from a reputed institute

What You’ll Work On :

Implementation and verification of scan architectures, JTAG (Joint Test Action Group), boundary scan, Memory BIST, LBIST, and ATPG (Automatic Test Pattern Generation)

Scan insertion, Design Rule Checking (DRC), and coverage analysis

Simulation debug with timing / SDF and post-silicon debug

Verilog / VHDL RTL coding, automation, and Mentor / Synopsys DFT toolsets

Debugging and root cause analysis for simulation and silicon-level failures

What We’re Looking For :

Proven DFT experience across multiple SoC designs (end-to-end)

Deep understanding of DFT methodologies and tool flows

Self-driven, detail-oriented, and collaborative professional

Excellent analytical, debugging, and communication skills

A curious mindset — eager to learn, explore, and push design boundaries

If you’re ready to take on challenging design-for-test projects and contribute to world-class semiconductor solutions, we’d love to connect with you!

📩 Apply now or DM - gagan@bestnanotech.in