Manager, Advanced Packaging Design Enablement Engineering (APDEE)

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Advanced Packaging Technology Development org is seeking an experienced and technically strong Die Design & Layout Manager to lead our die design and layout engineering function in support of our High Bandwidth Memory (HBM) packaging program. This role sits at the critical intersection of silicon design and advanced packaging, responsible for defining and executing die-level design strategy that enables world-class HBM product integration.

You will lead a team of die design and layout engineers, own the die design methodology and sign-off flow, and serve as the primary technical bridge between silicon design, packaging, process integration, and product engineering teams. Your work directly impacts the performance, yield, reliability, and time-to-market of next-generation HBM products used in AI, HPC, and data center applications.

Key Responsibilities

Team Leadership & Management
Lead, mentor, and grow a team of die build and layout engineers across multiple experience levels.
Define team goals, individual development plans, and performance expectations aligned with program breakthroughs
∙ Build team capability in advanced packaging-aware layout techniques, 3D integration design rules, and DFT-aware layout
∙ Own the end-to-end die design and layout strategy for HBM die programs, from concept through tape-out and post-silicon validation
∙ Define die floorplanning strategy including TSV grid placement, micro-bump array layout, power domain partitioning, and KOZ management
∙ Establish and maintain die design rules in alignment with foundry PDK requirements and advanced packaging process constraints

Technical Functional Roles & Responsibilities

• PWF Reticles Design and tapeout

• Developing DFTs in test vehicles for packaging related fail modes

• Co-work with HIG-HBM DTPCO, HIG-HBM team for developing test structures for live die

• Design rules management, Process Design rules for PWF , wafer thinning and dicing, die stacking etc

• BEOL Design - mainly engagement with FE Integration teams

• Engagement with Scribe Design team to capture Advanced Packaging requirements and Review

• TSV design engagement with HIG-HBM DTPCO teams ( electrical , thermal and mechanical performance)

• Creationand Maintenance of DFMEA related to advacned packaging process steps like PWF, die stacking etc

•Perform Electrical Simulations to understand the fail mode mechanism

Required Qualifications
Education
∙ Masters or PhD degree in Electrical Engineering, Computer Engineering, or related field required

Experience
∙ 10+ years of experience in die design and physical layout engineering
∙ 5+ years in a lead or management role overseeing layout engineering teams
∙ Direct hands-on experience with HBM, 3D-IC, or advanced packaging programs (CoWoS, SoIC, FOVEROS, or equivalent)
∙ Proven experience with TSV-based die design including KOZ management, micro-bump layout, and backside RDL

Technical Skills
∙ Deep expertise in physical design and layout using industry-standard EDA tools (Cadence Virtuoso, Innovus, Mentor Calibre, Synopsys IC Compiler)
∙ Strong knowledge of DRC/LVS/ERC sign-off flows and foundry PDK rule interpretation
∙ Solid understanding of TSV design rules, stress modeling implications, and 3D integration layout constraints
∙ Working knowledge of DFT structures relevant to advanced packaging
∙ Familiarity with JEDEC HBM specifications (HBM2E, HBM3, HBM3E)
∙ Understanding of power integrity, signal integrity, and thermal considerations at the die-package interface
Experience with parasitic extraction and design-focused optimization for high-speed memory interfaces

Preferred Qualifications

∙ Experience with hybrid bonding or direct bond interconnect (DBI) die design constraints
∙ Familiarity with chiplet architecture and disaggregated die design for heterogeneous integration
∙ Knowledge of HBM assembly (TCB, underfill, wafer thinning)
∙ Experience with layout automation scripting (Skill, Python, Tcl) for template generation and DRC waiver management
∙ Exposure to reliability physics relevant to advanced packaging: electromigration, stress voiding, thermo-mechanical degradation
∙ Published work or patents in advanced packaging, 3D-IC design, or memory interface design