#hiring#DV#designverification#opentowork#bangalorejobs
We&aposre looking for experienced DV Engineers to join our team!
Requirements :
✅ 5+ years in ASIC / SoC Design Verification
✅ Strong in SystemVerilog and UVM
✅ Experience with PCIe, Ethernet,DDR, AXI, or similar protocols
✅ Good debugging and scripting skills (Python / Perl / TCL)
Why Join Us
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Skills Required
Axi, Ddr, Perl, Pcie, Ethernet, Uvm, systemverilog, Python, Tcl
Design Verification Engineer • Bengaluru / Bangalore, India