Staff Engineer

Looking for an experienced senior verification engineer with 8-10 years of experience in ASIC/SOC/IP/block level functional verification using system verilog/UVM.

The ideal candidate will have strong command of UVM, advanced UVM and system verilog

Key responsibilities:

• Develop a comprehensive test plan, complete test-bench and robust verification environment including interface agents and scoreboard in UVM.
• Possess deep knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB.
• Strong debugging skills to address TB issues quickly and test failures.
• Take responsibility for verification closure by addressing coverage and managing bug reports.
• Proficiency in using industry standard verification tools such as Questa, VCS or ModelSim.
• Experience with scripting languages like python, perl or TCL for automation tasks.
• Able to track & manage Daily and weekly progress and manage a team of 6 to 7 Engineers.
• Interact with the customer on the tasks and status updates.

Skills Required
Tcl, System Verilog, Vcs, Uvm, Modelsim, Questa, Perl, Python