Senior Principal Logic Design Engineer ( Bangalore )

Senior Principal Logic Design Engineer

Location : Bangalore

We are a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing

As a SPE Logic Design Engineer, you’ll play a pivotal role in designing and implementing the world’s best Registered Clocking Driver (RCD) products. In this full-time role, you’ll report directly to our Logic Design Manager. Our MIC IDC is dedicated to leverage over three decades of high-performance memory expertise to deliver cutting-edge memory interface chipset solutions, enhancing memory bandwidth and capacity for data centers and client applications alike, and your contributions will be instrumental in RCD product development.

We offer a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.

Responsibilities

• Understand the spec requirements and convert into a micro architecture specification.
• Realize the RTL design using Verilog / System Verilog.
• Works with verification teams in defining the test plan and reviews the test coverage.
• Does pre implementation design checks like lint, CDC, RDC, constraint validation.
• Works with physical design team in defining the design and timing constraints and driving implementation till timing closure.
• Interact with cross functional circuit teams for new product development
• Participate in Architecture level discussions to define the specifications.
• Post silicon validation support in bringing up parts

Qualifications

Contact : Uday

Mulya Technologies

muday_bhaskar@yahoo.com

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