Asic Design Verification Engineer

Role Overview :

We are looking for Senior ASIC Design Verification Engineers with strong expertise in System Verilog (SV) and UVM methodology . The ideal candidate will have hands-on experience in SoC and IP-level verification across multiple domains, along with good scripting skills. Exposure to C language is a plus.

Key Responsibilities :

• Develop and execute verification plans for SoC and IP-level designs.
• Build and maintain test benches using System Verilog and UVM .
• Perform functional verification , including simulation, coverage analysis, and debugging.
• Collaborate with design and architecture teams to ensure verification completeness .
• Automate verification flows using scripting languages (Python, Perl, Shell, etc.).
• Analyze and report coverage metrics and ensure compliance with verification goals.

Required Skills :

Good to Have :

Education :

Bachelor’s or Master’s degree in Electronics, Electrical, or Computer Engineering or related field.