Lead Dft Engineer

Job Title : Lead DFT Engineer

Experience : 7+ Years

Location : Bangalore

Employment Type : Full-time

Industry : Semiconductors / ASIC / SoC Design

Job Summary :

We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC / ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.

Key Responsibilities :

• Define and drive DFT strategy and architecture for multiple ASIC / SoC projects.
• Lead implementation and verification of DFT features like :
• Scan insertion and compression (e.G., EDT)
• ATPG pattern generation and fault grading
• MBIST and Logic BIST insertion and validation
• Boundary scan (IEEE 1149.1 / 1149.6), IJTAG (1687)
• Manage end-to-end DFT flow — from RTL to gate-level netlist and silicon bring-up.
• Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.
• Perform pattern generation, fault simulation, and debug test coverage gaps.
• Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.
• Support silicon bring-up, test vector validation on ATE, and yield optimization.
• Mentor and guide junior DFT engineers;

conduct design reviews and training sessions.

Required Skills and Experience :

Preferred Qualifications :

Why Join Us?

Interested can share CV to sharmila.b@acldigital.com