Collaborate with cross-function al teams to develop and implement layout designs for analog and mixed-signal (A&MS) integrated circuits.
- Create and optimize layout designs using industry-stand ard EDA tools.
- Perform physical verification and design rule checks to ensure design integrity and manufacturabil ity.
- Participate in design reviews and provide feedback to improve design quality.
- Work closely with circuit designers to understand design specifications and constraints.
- Contribute to the development and enhancement of layout design methodologies and best practices.
- Stay updated with the latest industry trends and advancements in A&MS layout design.
The Impact You Will Have :
Ensure the delivery of high-quality layout designs for PVT Sensor IP development, integral to SOC subsystems.Enhance the manufacturabil ity and reliability of our silicon lifecycle monitoring solutions.Drive innovation in layout design methodologies and best practices.Collaborate effectively with circuit designers to meet design specifications and constraints.Contribute to the overall success of the rapidly expanding PVT IP group.Support Synopsys leadership in the market for process, voltage, temperature, current, and droop sensors.What You ll Need :
Bachelor s or master s degree in electrical engineering or a related field.5+ years of experience in A&MS layout design for integrated circuits.Proficiency in industry-stand ard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler.Exceptional knowledge of layout design methods, techniques, and methodologies.Experience with physical verification tools, such as Calibre or Assura.Understanding of semiconductor process technologies and their impact on layout design.Excellent problem-solvin g and systematic skills.Ability to work effectively in a team-oriented environment.Good communication and interpersonal skills.Skills Required
Cadence Virtuoso, semiconductor process technology