Design Verification Engineer

We are looking Verification engineer with 5-8 years experience to support our client in Bangalore.,

Pls share your resume if you have only available within Immediate to max 30 days notice.

Mention your notice period details : 30 days

Company : Hays ( https : / / www.haysplc.com / ) – Payroll

Location; Bangalore

Role; Verification engineer

Payroll; Hays

Mode of Interview; 1st round virtual / 2nd F2F

Experience level; 5-8 years

Job Description

Experience : 5-8 years

Responsibilities :

• Verification engineer with a knowledge of SoC integration verification, SoC scenario verification, SoC performance verification, CHI / DDRx / LPDDRx / AI accelerator integration verification in SoC RTL.
• Your key responsibilities will include writing test plans, defining test methodologies, developing C based software tests, SystemVerilog / Verilog testbenches and tests, and debugging of test failures and issues.
• Working with project management and leads on planning tasks, schedules, and reporting progress.
• Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development.

Required Skills and Experience :

Note : This position is on Hays payroll.