Sr ASIC Verification Engineer

Skills :

• Participated in the successful verification of a complex SoC or ASIC
• Mastering UVM or equivalent verification methodology
• Proficient developer of Constraint-Random / Coverage-Driven verification environments in SystemVerilog / C ++ (drivers / monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergrourp / SVA) Strong knowledge of simulation tools and coverage database visualization tools Developed test plans that helped identifying sharp functional defects
• efficiency in problem solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints Experienced in improving processes and methodologies Experience in managing tasks for a small team

Required minimum experience :

• 7 years

Skills Required

C++, Soc, Simulation, Asic verification, Uvm, Communication Engineering