Lead Soc Verification Engineer

Eteros Technolgies is Seeking a Senior / Lead Verification Engineer with strong expertise in simulation environment migration, debugging, and coverage analysis . The role involves migrating IP and SoC-level verification environments between Cadence Xcelium and Synopsys VCS , ensuring simulation stability, functional correctness, and coverage closure for complex designs involving ARM Cortex, PCIe , and other high-speed protocols.

Key Responsibilities

• Environment Migration :

Migrate SystemVerilog / UVM testbenches between Xcelium and VCS.

Resolve simulator-specific issues (macros, DPI, coverage differences) .

Verify PCIe at IP / SoC levels – LTSSM bring-up, PIPE / PHY interface, protocol compliance.

Debug link training, power management, and reset issues. Integrate and analyze VIPs (Synopsys / Cadence).

Set up and run GLS with / without timing.

Debug timing violations, X-propagation, and reset mismatches. Correlate RTL vs GLS for sign-off.

Automate regressions using Makefiles, Python, Perl on LSF / Jenkins.

Integrate IPs into ARM Cortex-based SoC environments.

Debug UVM / DUT interface failures and analyze assertion, protocol, and timing issues.

Track and close functional / code coverage using IMC, Verdi, or Verisium tools.

Required Skills

Qualifications