Design Verification Engineer
TEK Inspirations LLCBangalore5 days ago
Job description5+ years of experience in Design Verification. Strong proficiency in SystemVerilog and UVM methodology. Solid understanding of AMBA protocols (AXI, AHB, APB). Hands-on experience with CPU architectures, PCIe, or CXL. Exposure to SoC / subsystem-level simulation and integration. Strong debugging and problem-solving abilities. Familiarity with Gate-Level Simulations (GLS) is preferred. Excellent communication and collaboration skills.
Description :
Key Responsibilities :
- Define, develop, and execute SoC / subsystem-level verification plans.
- Design and maintain SystemVerilog / UVM-based testbenches for complex IPs and interfaces.
- Verify interfaces such as CPU, PCIe, and CXL, ensuring functionality, performance, and coverage.
- Drive coverage closure, regression testing, and quality sign-off.
- Collaborate closely with design and architecture teams in a fast-paced environment.
- Participate in Gate-Level Simulations (GLS) and debugging activities.
Key Skills & Qualifications :
(ref : hirist.tech)
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Design Verification Engineer • Bangalore