PCIe Verification Lead

PCIe Verification : Lead the verification of PCIe (PCI Express) interface designs, ensuring compliance with PCIe protocol standards (e.G., PCIe Gen 3 / 4 / 5 / 6, USB3, etc.).

Testbench Development : Develop and implement scalable, reusable, and efficient testbenches for PCIe designs using SystemVerilog, UVM (Universal Verification Methodology), and other industry-standard verification methodologies.

Protocol Compliance : Ensure that the PCIe designs conform to PCIe protocol specifications, including transaction layers, link training, error handling, and power management.

Verification Plan Creation : Create detailed verification plans for PCIe designs based on specifications and requirements, ensuring full coverage and correctness of the design.

Simulation & Debugging : Perform simulations and debugging using tools like Questa, VCS, or ModelSim to identify design issues. Use advanced debugging techniques, including waveform analysis and code coverage, to ensure design correctness.

Regression Testing : Set up and manage regression testing for continuous validation of PCIe functionality, tracking and resolving any failures.

Verification Coverage : Ensure thorough verification of all design corner cases, including protocol edge cases, power states, and interoperability scenarios. Achieve high coverage metrics (code, functional, and protocol coverage).

Formal Verification : Implement and use formal verification techniques to ensure correctness of the most critical PCIe components, such as link establishment, transaction layer, and error recovery mechanisms.