Physical Design Manager

Hyderabad

About Us

We are a technology consulting company delivering best-in class Chip Design Services.

Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow.

Chip Design Services

Analog IP Design

Foundation - OpAmp, Bandgap

IOs - GPIO, I2C, LVDS

Clocking - PLL

Power - LDO

SoC Design

RTL Design, Integration, Lint / CDC / RDC, UPF

IP / SoC UVM Verification

PPA, Synthesis, Constraints Management

Physical Design, Timing Closure, ECOs

Sign-off - Timing, Power, EM / IR, DRC / LVS / ERC

Message

About the job

As ASIC Physical Design Lead you will be leading the design of IP / SoC in advanced process technologies, serving global Semiconductor product MNC clients.

Job Summary :

We are looking for an ASIC Physical Design Lead with extensive experience in timing closure and full-chip physical design. The candidate should be adept at interacting with the packaging team and managing tasks such as pads log, bump placement, and RDL routing.

Key Responsibilities :

• Lead the physical design of complex ASIC projects from Netlist to GDSII.
• Perform timing closure tasks including synthesis, place and route, and static timing analysis.
• Oversee full-chip physical design processes, including floor planning, power grid design, clock tree synthesis, and signal integrity analysis.
• Collaborate with the packaging team to ensure seamless integration of the chip design with the package, including pads log management, bump placement, and RDL routing.
• Mentor junior engineers and guide them on physical design methodologies.
• Drive innovation and efficiency in physical design workflows.

Qualifications :

Contact : Uday Bhaskar

Mulya Technologies

"Mining the Knowledge Community"

Email id :