Senior Physical Design Engineer

Location : Hybrid

Job Type : Full-Time

Posted Date : 6 / 30 / 2025

About The Role

Job Overview : We are seeking a Senior Physical Design Engineer with strong expertise in Netlist-to-GDSII implementation and experience working on advanced submicron technology nodes. The role demands in-depth knowledge of industry-standard EDA tools and a solid grasp of timing closure and physical verification processes.

Key Responsibilities :  Drive full Netlist-to-GDSII flow : floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off.  Perform Static Timing Analysis (STA) and ensure timing closure across all design corners.  Execute power integrity and physical verification checks (LVS, DRC).  Collaborate closely with cross-functional teams (RTL, STA, packaging, and DFT).  Handle complex designs on 28nm and below technology nodes.

Must-Have Skills  Strong hands-on experience with : o Synopsys / Cadence tools : Innovus, ICC2, Primetime, PT-PX, Calibre o Physical Design Methodologies : Floorplanning, Placement, CTS, Routing, STA  Proficiency in : o Timing constraints and closure o Tcl / Tk / Perl scripting o Submicron nodes (28nm and below) Good to Have  Familiarity with Fusion Compiler  Broader understanding of signal and power integrity  Experience in workflow automation and tool scripting

If you are interested in this role, please mail your resume to [HIDDEN TEXT] or [HIDDEN TEXT].

Skills Required

Cadence Tools, floorplanning, Routing, Perl Scripting, primetime, Placement, Tk, Synopsys, Tcl