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Digital Design Engineer

Digital Design Engineer

ConfidentialBengaluru / Bangalore, India
5 days ago
Job description

Job Title : Digital Design Engineer

Work Location : Bangalore

Experience Required : 6 – 10 years

Job Description

The AsiaPac Design Enablement Engineering Support team focuses on implementing design methodologies and providing tactical support for SoC (System-on-Chip) design development across AsiaPac.

As a Design Engineer (Digital – III) , the candidate will play a key role in deploying, maintaining, and supporting design flows and tools used in integrated circuit (IC) development. The role requires close collaboration with global DE Engineering Support, design flow, technology development, and IT teams.

The candidate will serve as the primary liaison for specific business design teams, ensuring proactive coordination, problem resolution, and implementation of new technical solutions to enhance IC design productivity.

Key Responsibilities

  • Act as the Project Liaison for assigned business unit design teams, understanding their design flow requirements and implementing tailored solutions.
  • Provide front-line support for design flow-integrated tools : diagnosing issues, troubleshooting, and resolving tool-related problems.
  • Develop and customize design automation scripts and utilities in collaboration with global DE flow and technology development teams.
  • Deploy new design tools and methodologies as per project needs.
  • Conduct training sessions and provide continuous support to design teams on evolving design flows.
  • Serve as a technical interface with IT teams to address infrastructure dependencies and support issues.
  • Provide CAD expertise in specialized technical areas (digital backend, physical verification, or automation scripting).
  • Collaborate with global design teams and EDA tool vendors (Cadence, Synopsys, Mentor) to develop and optimize methodologies and design tools.

Technical Skills Required

Digital Backend Design :

  • Proficiency in Cadence tools : Innovus, Tempus, QRC, Voltus, Genus, Conformal LEC
  • Proficiency in Synopsys tools : ICC2, ICV, PrimeTime, Design Compiler (DC), Formality, PTPX
  • Physical Verification : Mentor Calibre or Cadence PVS
  • Low-Power Design & UPF Methodology exposure
  • Automation & Scripting

  • Strong programming in TCL, Shell, PERL, and Python
  • Infrastructure Knowledge

  • Solid understanding of IT infrastructure, EDA environment setup, and LSF (Load Sharing Facility)
  • Preferred Qualifications

  • Hands-on experience in SoC design enablement, CAD support, and flow automation
  • Strong collaboration and communication skills for cross-functional and cross-geography teamwork
  • Skills Required

    Digital Backend Design, EDA environment setup

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