FPGA Designer - VHDL / Verilog

Job :

• Design, architect, and develop FPGA RTL (VHDL / Verilog) logic and subsystems for high-speed serial protocols.
• Address FPGA design challenges such as CDC, multi-clock domains, timing closure, and SerDes-related issues.
• Drive timing closure and optimization using FPGA synthesis and implementation tools (Xilinx Vivado).
• Debug and validate FPGA and board-level issues, ensuring robust high-speed interface performance.
• Collaborate with global R&D teams to deliver production-ready FPGA solutions.
• Leverage AI-assisted tools (e.g., GitHub Copilot, LLM-based aids) to accelerate RTL development and productivity.

Requirements :

(ref : hirist.tech)