Sr.Design Verification Engineer

Job Title : IP / SOC Verification Engineer

Experience : 5+ Years

Location : Bengaluru / Hyderabad

Company : Tessolve Semiconductor

Notice Period : Immediate to 30 Days

Employment Type : Full-time / Permanent

About Tessolve

Tessolve Semiconductor, part of the Hero Group, is a leading engineering services company offering end-to-end silicon and system design solutions. Tessolve provides expertise across ASIC design, verification, post-silicon validation, and embedded software development — enabling customers to accelerate product development from concept to production.

Job Summary

Tessolve is looking for an experienced IP / SOC Verification Engineer with strong hands-on experience in SystemVerilog / UVM-based functional verification . The candidate will contribute to verification planning, testbench development, simulation, and debug activities for complex IP and SoC designs.

Key Responsibilities

• Develop and maintain UVM / SystemVerilog testbenches for IP and SOC-level verification.
• Define verification plans , test strategies, and coverage goals.
• Implement constrained-random, directed, and assertion-based tests .
• Integrate multiple IPs at SOC level and verify system functionality.
• Analyze simulation failures, debug issues, and work closely with design teams for root cause analysis.
• Ensure functional and code coverage closure and regression automation.
• Participate in design / verification reviews and contribute to methodology improvements.

Required Skills and Qualifications

Good to Have

Why Tessolve

Application Details