Timing Closure Engineer

Role : STA Engineer

Experience : 3+ Years

Location : Bangalore (Onsite)

Notice Period : Immediate to 30 Days / Serving Notice

Key Responsibilities :

• Perform Static Timing Analysis (STA) at block and full-chip levels across multiple design stages (synthesis, P&R, sign-off).
• Develop, validate, and maintain timing constraints (SDC files) for complex SoC and IP-level designs.
• Collaborate with RTL, Physical Design, and Verification teams to ensure proper constraint definition and timing closure.
• Analyze and debug setup / hold violations , false paths, and timing exceptions across corners and modes.
• Drive timing closure using advanced analysis techniques and ECO implementation.

Why Join Us :